MC9S12NE64V1 Datasheet, PDF (159/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

4.4.2 System Clocks Generator
Functional Description
PLLSEL or SCM
PHASE
LOCK
LOOP
PLLCLK
1
0
EXTAL
OSCCLK
OSCILLATOR
XTAL
Clock
Monitor
SCM
1
0
SYSCLK
WAIT(SYSWAI),
STOP
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
WAIT(COPWAI),
STOP(PSTP,PCE),
COP enable
WAIT(SYSWAI),
STOP
Gating
Condition
= Clock Gate
STOP(PSTP)
WAIT(CWAI,SYSWAI),
STOP
Core Clock
÷2
CLOCK PHASE
Bus Clock
GENERATOR
RTI
COP
Oscillator
Clock
Oscillator
Clock
(running during
Pseudo-Stop Mode
Figure 4-17. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 4-17). The gating condition placed on
top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting
of the respective configuration bits.
The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The
memory blocks use the bus clock. If the MCU enters self-clock mode (see Section 4.4.7.2, “Self-Clock
Mode”), oscillator clock source is switched to PLLCLK running at its minimum frequency f_SCM. The bus
clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.
The core clock is twice the bus clock as shown in Figure 4-18. But note that a CPU cycle corresponds to
one bus clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
159