MC9S12NE64V1 Datasheet, PDF (128/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.5.3 Data Direction Register (DDRJ)
Module Base + $22
Bit 7
6
5
4
Read:
Write:
DDRJ7
DDRJ6
0
0
Reset:
0
0
—
—
3
DDRJ3
0
2
DDRJ2
0
1
DDRJ1
0
Bit 0
DDRJ0
0
= Reserved or unimplemented
Figure 3-33. Port J Data Direction Register (DDRJ)
Read:Anytime.
Write:Anytime.
This register configures port pins J[7:6]and PJ[3:0] as either input or output.
DDRJ[7:6][3:0] — Data Direction Port J
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ
or PTIJ registers, when changing the DDRJ register.
If the IIC is enabled, It controls the direction of SCL and SDA and the corresponding DDRJ[7:6] bits have
no effect on their I/O direction. Refer to the IIC block description chapter for details.
If the EMAC MII external interface is enabled, It controls the direction of MDC, MDIO, CRS and COL
and the corresponding DDRJ[3:0] bits have no effect on their I/O direction. Refer to the EMAC block
description chapter for details.
3.3.2.5.4 Reduced Drive Register (RDRJ)
Module Base + $23
Bit 7
6
5
4
Read:
Write:
RDRJ7
RDRJ6
0
0
Reset:
0
0
—
—
3
RDRJ3
0
2
RDRJ2
0
1
RDRJ1
0
Bit 0
RDRJ0
0
= Reserved or unimplemented
Figure 3-34. Port J Reduced Drive Register (RDRJ)
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRJ[7:6][3:0] — Reduced Drive Port J
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
MC9S12NE64 Data Sheet, Rev. 1.1
128
Freescale Semiconductor