MC9S12NE64V1 Datasheet, PDF (56/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 1 MC9S12NE64 Device Overview
1.2.3.52 PS2 / SCI1_RXD — Port S I/O Pin 2
PS2 is a general-purpose I/O. When the serial communications interface 1 (SCI1) receiver is enabled, PS2
becomes the receive pin RXD of SCI1. While in reset and immediately out of reset, the PS2 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.53 PS1 / SCI0_TXD — Port S I/O Pin 1
PS1 is a general-purpose I/O. When the serial communications interface 0 (SCI0) transmitter is enabled,
PS1 becomes the transmit pin, TXD, of SCI0. While in reset and immediately out of reset, the PS1 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.54 PS0 / SCI0_RXD — Port S I/O Pin 0
PS0 is a general-purpose I/O. When the serial communications interface 0 (SCI0) receiver is enabled, PS0
becomes the receive pin RXD0 of SCI0. While in reset and immediately out of reset, the PS0 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.55 PT[7:4] / IOC1[7:4] — Port T I/O Pins [7:4]
PT[7:4] are general-purpose I/O pins. While the timer system 1 (TIM1) is enabled, these pins can also be
configured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and immediately
out of reset, the PT[7:4] pins are configured as a high-impedance input pins. See the port integration
module (PIM) PIM_9NE64 block description chapter and the TIM_16B4C block description chapter for
information about pin configurations.
1.2.3.56 PHY_TXP — EPHY Twisted Pair Output +
Ethernet twisted pair output pin. This pin is hi-z out of reset.
1.2.3.57 PHY_TXN — EPHY Twisted Pair Output –
Ethernet twisted pair output pin. This pin is hi-z out of reset.
1.2.3.58 PHY_RXP — EPHY Twisted Pair Input +
Ethernet twisted pair input pin. This pin is hi-z out of reset.
1.2.3.59 PHY_RXN — EPHY Twisted Pair Input –
Ethernet twisted pair input pin. This pin is hi-z out of reset.
MC9S12NE64 Data Sheet, Rev 1.0
56
Freescale Semiconductor