MC9S12NE64V1 Datasheet, PDF (193/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

6.3.2.9 Timer Control Register 3 (TCTL3)
Memory Map and Register Definition
R
W
Reset
7
EDG7B
0
6
EDG7A
5
EDG6B
4
EDG6A
3
EDG5B
2
EDG5A
0
0
0
0
0
Figure 6-15. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
Read: Anytime
Write: Anytime.
Table 6-10. TCTL3/TCTL4 Field Descriptions
Field
7:0
EDGnB
EDGnA
Description
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 6-11. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
193