MC9S12NE64V1 Datasheet, PDF (151/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
Table 4-4. CLKSEL Field Descriptions (continued)
Field
Description
1
RTIWAI
0
COPWAI
RTI Stops in Wait Mode Bit — Write: anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
4.3.2.7 CRG PLL Control Register (PLLCTL)
This register controls the PLL functionality.
R
W
Reset
7
CME
1
6
5
4
3
2
0
PLLON
AUTO
ACQ
PRE
1
1
1
0
0
= Unimplemented or Reserved
Figure 4-10. CRG PLL Control Register (PLLCTL)
1
PCE
0
0
SCME
1
Read: anytime
Write: refer to each bit for individual write conditions
Table 4-5. PLLCTL Field Descriptions
Field
7
CME
6
PLLON
5
AUTO
4
ACQ
Description
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock
mode.
Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause
unpredictable operation of the MCU.
Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss
of clock will not be detected.
Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the
PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.
0 PLL is turned off.
1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low
bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime
except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1.
0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.
1 Automatic mode control is enabled and ACQ bit has no effect.
Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect.
0 Low bandwidth filter is selected.
1 High bandwidth filter is selected.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
151