MC9S12NE64V1 Datasheet, PDF (20/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 1 MC9S12NE64 Device Overview
• Timer module (TIM)
— 4-channel timer
— Each channel configurable as either input capture or output compare
— Simple PWM mode
— Modulo reset of timer counter
— 16-bit pulse accumulator
— External event counting
— Gated time accumulation
• Serial interfaces
— Two asynchronous serial communications interface (SCI)
— One synchronous serial peripheral interface (SPI)
— One inter-IC bus (IIC)
• Ethernet Media access controller (EMAC)
— IEEE 802.3 compliant
— Medium-independent interface (MII)
— Full-duplex and half-duplex modes
— Flow control using pause frames
— MII management function
— Address recognition
– Frames with broadcast address are always accepted or always rejected
– Exact match for single 48-bit individual (unicast) address
– Hash (64-bit hash) check of group (multicast) addresses
– Promiscuous mode
• Ethertype filter
• Loopback mode
• Two receive and one transmit Ethernet buffer interfaces
• Ethernet 10/100 Mbps transceiver (EPHY)
— IEEE 802.3 compliant
— Digital adaptive equalization
— Half-duplex and full-duplex
— Auto-negotiation next page ability
— Baseline wander (BLW) correction
— 125-MHz clock generator and timing recovery
— Integrated wave-shaping circuitry
— Loopback modes
• CRG (clock and reset generator module)
— Windowed COP watchdog
— Real-time interrupt
MC9S12NE64 Data Sheet, Rev 1.0
20
Freescale Semiconductor