MC9S12NE64V1 Datasheet, PDF (349/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

RXP
RXN
10BASE-T
RECEIVER
POLARITY CORRECTION
SQUELCH
LINK DETECT
External Signal Descriptions
CLOCK RECOVERY
MANCHESTER DECODE
100BASE-TX
RECEIVER
100BASE-TX
LOOPBACK
TXP
TXN
10BASE-T
DRIVER
100BASE-TX
DRIVER
VGA CONTROL
(COARSE EQUALIZER)
DIGITAL EQUALIZER
SLICER
TIMING CONTROL
BLW CONTROL
10BASE-T
DIG LOOP B
100BASE-TX
DIG LOOP B
SCRAMBLER
MLT-3 ENCODE
MLT-3 DECODE
DESCRAMBLER
4B/5B
DECODE
MII
AUTO
NEGOTIATE
COLLISION
CARRIER SENSE
MANCHESTER ENCODER
DIGITAL WAVE SHAPING
4B / 5B
ENCODE
MII
LOOPBACK
RBIAS
VOLTAGE/ CURRENT
REFERENCES
10BASE-T
PLL
100BASE-TX
PLL
REF
CLOCK
MANAGEMENT
(MII)
CONFIGURATION
REGISTERS
MDIO
Figure 12-2. PHY Sub Block Diagram
12.2 External Signal Descriptions
This section contains the EPHY external pin descriptions.
12.2.1 PHY_TXP — EPHY Twisted Pair Output +
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.2 PHY_TXN — EPHY Twisted Pair Output –
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.3 PHY_RXP — EPHY Twisted Pair Input +
Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
349