MC9S12NE64V1 Datasheet, PDF (278/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 9 Serial Peripheral Interface (SPIV3)
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease I_DD current.
BaudRateDivisor = (SPPR + 1) • 2^{(SPR + 1)}
Figure 9-11. Baud Rate Divisor Equation
9.4.5 Special Features
9.4.5.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and
MODFEN bit as shown in Table 9-3.
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multimaster
system because the mode fault feature is not available for detecting system
errors between masters.
9.4.5.2 Bidirectional Mode (MOSI or MISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see Table 9-9). In
this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
Table 9-9. Normal Mode and Bidirectional Mode
When SPE = 1
Master Mode MSTR = 1
Slave Mode MSTR = 0
Normal Mode
SPC0 = 0
Serial Out
SPI
Serial In
MOSI
MISO
Serial In
SPI
Serial Out
MOSI
MISO
Bidirectional Mode
SPC0 = 1
Serial Out
SPI
Serial In
BIDIROE
MOMI
Serial In
SPI
Serial Out
BIDIROE
SISO
MC9S12NE64 Data Sheet, Rev. 1.1
278
Freescale Semiconductor