MC9S12NE64V1 Datasheet, PDF (227/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Functional Description
7.4.2 Digital Sub-Block
This subsection explains some of the digital features in more detail. See register descriptions for all details.
7.4.2.1 External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to
be edge or level sensitive with polarity control. Table 7-23 gives a brief description of the different
combinations of control bits and their effect on the external trigger function.
ETRIGLE
X
X
0
0
1
1
Table 7-23. External Trigger Control Bits
ETRIGP
X
X
0
1
0
1
ETRIGE
0
0
1
1
1
1
SCAN
0
1
X
X
X
X
Description
Ignores external trigger. Performs one
conversion sequence and stops.
Ignores external trigger. Performs
continuous conversion sequences.
Falling edge triggered. Performs one
conversion sequence per trigger.
Rising edge triggered. Performs one
conversion sequence per trigger.
Trigger active low. Performs
continuous conversions while trigger
is active.
Trigger active high. Performs
continuous conversions while trigger
is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received. In both
cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger
circuitry.
NOTE
The conversion results for the external trigger ATD channel 7 have no
meaning while external trigger mode is enabled.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
227