MC9S12NE64V1 Datasheet, PDF (545/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Introduction
B.1.2 Power Supply Notes
A 3.3-V power supply is required. This power supply shall be compatible with Table A-7. Supply
Current Characteristics.
B.1.3 Clocking Notes
For basic operation of the MC9S12NE64, a 25-MHz crystal is required to provide the clock input to the
integrated PHY. The crystal must connect to the MC9S12NE64 in a Pierce configuration by the XTAL and
EXTAL pins as shown in Figure B-1.
In addition to providing a 25-MHz crystal input, to operate at 100 Mbps, the internal bus clock must be
configured as shown in the EPHY electrical characteristics.
B.1.4 EPHY Notes
Figure B-2 provides a close-up view of the EPHY pin connections to a high-speed LAN magnetics
isolation module and RJ45 Ethernet connector.
Figure B-2. Ethernet Interface Circuitry
B.1.5 EPHY LED Indicator Notes
The EPHY can be configuring by software to drive indicator pins (PTL[5:0]) automatically by setting the
LEDEN bit of the EPHY EPHYCTL0 register. When LEDEN = 1, PTL[5:0] pins are dedicated to the
EPHY.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
545