MC9S12NE64V1 Datasheet, PDF (269/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

SPPR2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Memory Map and Register Definition
Table 9-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued)
SPPR1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SPPR0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SPR2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SPR1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SPR0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud Rate
Divisor
1280
12
24
48
96
192
384
768
1536
14
28
56
112
224
448
896
1792
16
32
64
128
256
512
1024
2048
Baud Rate
19.53 kHz
2.08333 MHz
1.04167 MHz
520.83 kHz
260.42 kHz
130.21 kHz
65.10 kHz
32.55 kHz
16.28 kHz
1.78571 MHz
892.86 kHz
446.43 kHz
223.21 kHz
111.61 kHz
55.80 kHz
27.90 kHz
13.95 kHz
1.5625 MHz
781.25 kHz
390.63 kHz
195.31 kHz
97.66 kHz
48.83 kHz
24.41 kHz
12.21 kHz
NOTE
In slave mode of SPI S-clock speed DIV2 is not supported.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
269