MC9S12NE64V1 Datasheet, PDF (263/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
9.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
9.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when its configured as a master and its used as an input to receive the slave select
signal when the SPI is configured as slave.
9.2.4 SCK — Serial Clock Pin
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of
slave.
9.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the SPIV3 is given below in Table 9-1. The address listed for each register is the sum
of a base address and an address offset. The base address is defined at the SoC level and the address offset
is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
9.3.1 Module Memory Map
Table 9-1. SPIV3 Memory Map
Address
Use
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
SPI Control Register 1 (SPICR1)
SPI Control Register 2 (SPICR2)
SPI Baud Rate Register (SPIBR)
SPI Status Register (SPISR)
Reserved
SPI Data Register (SPIDR)
Reserved
Reserved
1 _{Certain bits are non-writable.}
2 _{Writes to this register are ignored.}
3 _{Reading from this register returns all zeros.}
Access
R/W
R/W¹
R/W¹
R²
— ^2,3
R/W
— ^2,3
— ^2,3
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
263