MC9S12NE64V1 Datasheet, PDF (432/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 16 Module Mapping Control (MMCV4)
16.3.2.7 Memory Size Register 0 (MEMSIZ0)
7
6
5
4
3
2
R REG_SW0
0
EEP_SW1 EEP_SW0
0
RAM_SW2
W
Reset
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 16-9. Memory Size Register 0 (MEMSIZ0)
1
RAM_SW1
—
0
RAM_SW0
—
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Table 16-7. MEMSIZ0 Field Descriptions
Field
Description
7
REG_SW0
Allocated System Register Space
0 Allocated system register space size is 1K byte
1 Allocated system register space size is 2K byte
5:4
Allocated System EEPROM Memory Space — The allocated system EEPROM memory space size is as
EEP_SW[1:0] given in Table 16-8.
2
Allocated System RAM Memory Space — The allocated system RAM memory space size is as given in
RAM_SW[2:0] Table 16-9.
Table 16-8. Allocated EEPROM Memory Space
eep_sw1:eep_sw0
00
01
10
11
Allocated EEPROM Space
0K byte
2K bytes
4K bytes
8K bytes
ram_sw2:ram_sw0
000
001
010
011
100
Table 16-9. Allocated RAM Memory Space
Allocated
RAM Space
2K bytes
4K bytes
6K bytes
8K bytes
10K bytes
RAM
Mappable Region
2K bytes
4K bytes
8K bytes²
8K bytes
16K bytes ²
INITRM
Bits Used
RAM[15:11]
RAM[15:12]
RAM[15:13]
RAM[15:13]
RAM[15:14]
RAM Reset
Base Address¹
0x0800
0x0000
0x0800
0x0000
0x1800
MC9S12NE64 Data Sheet, Rev. 1.1
432
Freescale Semiconductor