MC9S12NE64V1 Datasheet, PDF (209/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemente
R
d
W
ATDSTAT1
R CCF7
W
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
Unimplemente
R
d
W
ATDDIEN
R
IEN7
W
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
Unimplemente
R
d
W
PORTAD
R PTAD7
W
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Left Justified Result Data
Note: The read portion of the left justified result data registers has been divided to show the bit position when reading 10-bit
and 8-bit conversion data. For more detailed information refer to Section 7.3.2.13, “ATD Conversion Result Registers
(ATDDRx)”.
ATDDR0H
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
W
ATDDR0L
10-BIT BIT 1
BIT 0
0
0
0
0
0
0
8-BIT
U
U
0
0
0
0
0
0
W
ATDDR1H
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
ATDDR1L
10-BIT BIT 1
BIT 0
0
0
0
0
0
0
8-BIT
U
U
0
0
0
0
0
0
W
ATDDR2H
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
ATDDR2L
10-BIT BIT 1
BIT 0
0
0
0
0
0
0
8-BIT
U
U
0
0
0
0
0
0
W
ATDDR3H
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
= Unimplemented or Reserved
Figure 7-2. ATD Register Summary (Sheet 2 of 5)
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
209