MC9S12NE64V1 Datasheet, PDF (145/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
NOTE
Register address = base address + address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
4.3.2 Register Descriptions
This section describes in address order all the CRGV4 registers and their individual bits.
Register
Name
SYNR
REFDV
CTFLG
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTICTL
COPCTL
FORBYP
CTCTL
Bit 7
6
5
4
3
2
1
Bit 0
R
0
W
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
R
0
0
0
0
REFDV3 REFDV2 REFDV1 REFDV0
W
R
0
0
0
0
0
0
0
0
W
R
RTIF
W
PORF
LVRF
LOCKIF
LOCK
TRACK
SCMIF
SCM
R
0
RTIE
W
0
0
LOCKIE
0
0
SCMIE
R
PLLSEL
W
PSTP SYSWAI ROAWAI PLLWAI
CWAI
RTIWAI COPWAI
R
0
CME
PLLON AUTO
ACQ
PRE
PCE
SCME
W
R
0
W
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
R
0
0
0
WCOP RSBCK
CR2
CR1
CR0
W
R
0
0
0
0
0
0
0
0
W
R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 4-3. CRG Register Summary
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
145