MC9S12NE64V1 Datasheet, PDF (267/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

9.3.2.3 SPI Baud Rate Register (SPIBR)
Memory Map and Register Definition
7
6
5
4
3
R
0
0
SPPR2
SPPR1
SPPR0
W
2
SPR2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-5. SPI Baud Rate Register (SPIBR)
1
SPR1
0
0
SPR0
0
Read: anytime
Write: anytime; writes to the reserved bits have no effect
Table 9-6. SPIBR Field Descriptions
Field
Description
6:4
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 9-7. In master
SPPR[2:0] mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
2:0
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 9-7. In master mode,
SPR[2:0} a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 1) • 2^{(SPR + 1)}
The baud rate can be calculated with the following equation:
Baud Rate = BusClock ⁄ BaudRateDivisor
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
267