MC9S12NE64V1 Datasheet, PDF (195/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
Table 6-14. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
6.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
7
6
5
4
3
2
1
0
R
0
0
0
0
C7F
C6F
C5F
C4F
W
Reset
0
0
0
0
0
0
0
0
Figure 6-18. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 6-15. TRLG1 Field Descriptions
Field
7:4
C[7:4]F
Description
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clear a channel flag by writing one to it.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
195