MC9S12NE64V1 Datasheet, PDF (322/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 11 Ethernet Media Access Controller (EMACV1)
0 = No interrupt request is generated by this event.
RXACIE — Valid Frame Reception to Receive Buffer A Complete Interrupt Enable
1 = A valid frame reception to receive buffer A complete event causes a valid frame reception to
receive buffer A complete interrupt request.
0 = No interrupt request is generated by this event.
RXBCIE — Valid Frame Reception to Receive Buffer B Complete Interrupt Enable
1 = A valid frame reception to receive buffer B complete event causes a valid frame reception to
receive buffer B complete interrupt request.
0 = No interrupt request is generated by this event.
MMCIE — MII Management Transfer Complete Interrupt Enable
1 = An MII management transfer complete event causes an MII management transfer complete
interrupt request.
0 = No interrupt request is generated by this event.
LCIE — Late Collision Interrupt Enable
1 = A late collision event causes a late collision interrupt request.
0 = No interrupt request is generated by this event.
ECIE — Excessive Collision Interrupt Enable
1 = An excessive collision event causes an excessive collision interrupt request.
0 = No interrupt request is generated by this event.
TXCIE — Frame Transmission Complete Interrupt Enable
1 = A frame transmission complete event causes a frame transmission complete interrupt request.
0 = No interrupt request is generated by this event.
11.3.2.9 Software Reset (SWRST)
Module Base + $E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W MACRST
RESET:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-10. Software Reset (SWRST)
Read: Anytime.
Write: Anytime, but the user must not change this bit while BUSY is set.
MACRST — MAC Software Reset
Writing a 0 to this bit has no effect. This bit always reads 0.
When this bit is set, the equivalent of a hardware reset is performed but it is local to the EMAC. The
EMAC logic is initialized and all EMAC registers take their reset values. Any transmission/reception
currently in progress is abruptly aborted.
1 = EMAC is reset.
0 = Normal operation.
MC9S12NE64 Data Sheet, Rev. 1.1
322
Freescale Semiconductor