MC9S12NE64V1 Datasheet, PDF (270/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 9 Serial Peripheral Interface (SPIV3)
9.3.2.4 SPI Status Register (SPISR)
7
6
5
4
3
2
1
0
R SPIF
0
SPTEF
MODF
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. SPI Status Register (SPISR)
Read: anytime
Write: has no effect
Table 9-8. SPISR Field Descriptions
Field
7
SPIF
5
SPTEF
4
MODF
Description
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI Data Register.
This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data
Register.
0 Transfer not yet complete
1 New data copied to SPIDR
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write
to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored.
0 SPI Data register not empty
1 SPI Data register empty
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 9.3.2.2, “SPI Control Register 2 (SPICR2).” The flag is cleared automatically by a read of the SPI Status
Register (with MODF set) followed by a write to the SPI Control Register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
9.3.2.5 SPI Data Register (SPIDR)
7
6
5
4
3
2
R
Bit 7
6
5
4
3
2
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. SPI Data Register (SPIDR)
Read: anytime; normally read only after SPIF is set
Write: anytime
1
0
2
Bit 0
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
270
Freescale Semiconductor