MC9S12NE64V1 Datasheet, PDF (377/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Functional Description
12.4.5.2 Wait Mode
If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY will be powered down and
all internal MII registers reset to their default state. Upon exiting STOP mode the EPHY will exit the
power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers.
The MII registers must be re-initialized after the start-up delay (t_Start-up) has expired.
12.4.5.3 MII Power Down
This mode disconnects the PHY from the network interface (three-state receiver and driver pins).
Setting bit 0.11 of the port enters this mode. In this mode, the management interface is accessible but all
internal chip functions are in a zero power state.
In this mode all analog blocks except the PLL clock generator and band gap reference are in low power
mode. All digital blocks except the MDIO interface and management registers are inactive.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
377