MC9S12NE64V1 Datasheet, PDF (387/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 14
Interrupt (INTV1)
14.1 Introduction
This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform.
A block diagram of the interrupt sub-block is shown in Figure 14-1.
INT
WRITE DATA BUS
HPRIO (OPTIONAL)
HIGHEST PRIORITY
I-INTERRUPT
INTERRUPTS
XMASK
IMASK
INTERRUPT INPUT REGISTERS
AND CONTROL REGISTERS
READ DATA BUS
WAKEUP
RESET FLAGS
VECTOR REQUEST
QUALIFIED
INTERRUPTS
PRIORITY DECODER
INTERRUPT PENDING
VECTOR ADDRESS
Figure 14-1. INTV1 Block Diagram
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable
vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a
non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
387