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MC9S12NE64V1 Datasheet, PDF (136/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet | |||
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Chapter 3 Port Integration Module (PIM9NE64V1)
3.4.7 Port S
This port is associated with the serial SCI and SPI modules.
Port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI0, SCI1, and SPI
subsystems.
During reset, port S pins are conï¬gured as inputs with pull-up.
3.4.8 Port G
This port is associated with the EMAC module.
Port G pins PG[7:0] can be used either for general-purpose I/O or with the EMAC subsystems. Further the
Keypad Wake-Up function is implemented on pins G[7:0].
During reset, port G pins are conï¬gured as high-impedance inputs.
3.4.8.1 Interrupts
Port G offers eight general-purpose I/O pins with edge triggered interrupt capability in wired-or fashion.
The interrupt enable as well as the sensitivity to rising or falling edges can be individually conï¬gured on
per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins
conï¬gured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt ï¬ag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in STOP
or WAIT mode.
A digital ï¬lter on each pin prevents pulses (Figure 3-48) shorter than a speciï¬ed time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 3-47 and
Table 3-4).
Glitch, ï¬ltered out, no interrupt ï¬ag set
Valid pulse, interrupt ï¬ag set
tpign
tpval
Figure 3-47. Interrupt Glitch Filter on Port G, H, and J (PPS=0)
MC9S12NE64 Data Sheet, Rev. 1.1
136
Freescale Semiconductor
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