MC9S12NE64V1 Datasheet, PDF (50/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 1 MC9S12NE64 Device Overview
1.2.3.16 PK6 / XCS — Port K I/O Pin 6
PK6 is a general-purpose I/O pin. During MCU expanded modes of operation, while the EMK bit in the
MODE register is set to 1, this pin is used as an external chip select signal for most external accesses that
are not selected by ECS. There is an active pull-up on this pin while in reset and immediately out of reset.
The pull-up can be turned off by clearing PUPKE in the PUCR register. See the multiplexed external bus
interface (MEBI) block description chapter for further details. PK6 is not available in the 80-pin package
version.
1.2.3.17 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK[5:0] are general-purpose I/O pins. In MCU expanded modes of operation, when the EMK bit in the
MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external bus.
There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pull-up can be
turned off by clearing PUPKE in the PUCR register. See multiplexed external bus interface (MEBI) block
description chapter for further details. PK[5:0] are not available in the 80-pin package version.
1.2.3.18 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD[7:0] are the analog inputs for the analog-to-digital converter (ATD). They can also be configured as
general-purpose digital input. See the port integration module (PIM) PIM_9NE64 block description
chapter and the ATD_10B8C block description chapter for information about pin configurations.
1.2.3.19 PG7 / KWG7 — Port G I/O Pin 7
PG7 is a general-purpose I/O pin. It can be configured to generate an interrupt (KWG7) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PG7 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
for information about pin configurations.
1.2.3.20 PG6 / KWG6 / MII_RXER — Port G I/O Pin 6
PG6 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
receive error (MII_RXER) signal. It can be configured to generate an interrupt (KWG6) causing the MCU
to exit stop or wait mode. While in reset and immediately out of reset, the PG6 pin is configured as a
high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
1.2.3.21 PG5 / KWG5 / MII_RXDV — Port G I/O Pin 5
PG5 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the
receive data valid (MII_RXDV) signal. It can be configured to generate an interrupt (KWG5) causing the
MCU to exit stop or wait mode. While in reset and immediately out of reset, the PG5 pin is configured as
a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter
and the EMAC block description chapter for information about pin configurations.
MC9S12NE64 Data Sheet, Rev 1.0
50
Freescale Semiconductor