MC9S12NE64V1 Datasheet, PDF (309/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

External Signal Description
11.2.1 MII_TXCLK — MII Transmit Clock
The PHY provides this input clock, which is used as a timing reference for MII_TXD, MII_TXEN, and
MII_TXER. It operates at 25% of the transmit data rate (25 MHz for 100 Mbps or 2.5 MHz for 10 Mbps).
The EMAC bus clock frequency must be greater-than or equal-to MII_TXCLK.
11.2.2 MII_TXD[3:0] — MII Transmit Data
MII_TXD[3:0] is a transmit nibble of data to be transferred from the EMAC to the PHY. The nibble is
synchronized to the rising edge of MII_TXCLK. When MII_TXEN is asserted, the PHY accepts
MII_TXD[3:0], and at all other times, MII_TXD[3:0] is ignored. MII_TXD[0] is the least significant bit.
Table 11-1 summarizes the permissible encoding of MII_TXD[3:0], MII_TXEN, and MII_TXER.
Table 11-1. Permissible Encoding of MII_TXD, MII_TXEN, and MII_TXER
MII_TXEN
0
0
1
1
MII_TXER
0
1
0
1
MII_TXD[3:0]
0000 through 1111
0000 through 1111
0000 through 1111
0000 through 1111
Indication
Normal interframe
Reserved
Normal data transmission
Transmit error propagation
11.2.3 MII_TXEN — MII Transmit Enable
Assertion of this output signal indicates that there are valid nibbles being presented on the MII and the
transmission can start. This signal is asserted with the first nibble of the preamble, remains asserted until
all nibbles to be transmitted have been presented to the PHY, and is negated following the final nibble of
the frame.
11.2.4 MII_TXER — MII Transmit Coding Error
Assertion of this output signal for one or more clock cycles while MII_TXEN is asserted causes the PHY
to transmit one or more illegal symbols. MII_TXER is asserted if the ABORT command is issued during
a transmit. This signal transitions synchronously with respect to MII_TXCLK.
11.2.5 MII_RXCLK — MII Receive Clock
The PHY provides this input clock, which is used as a timing reference for MII_RXD, MII_RXDV, and
MII_RXER. It operates at 25% of the receive data rate (25 MHz for 100 Mbps or 2.5 MHz for 10 Mbps).
The EMAC bus clock frequency must be greater-than or equal-to MII_RXCLK.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
309