MC9S12NE64V1 Datasheet, PDF (536/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Appendix A Electrical Characteristics
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT²
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12
BIT 6 . . . 1
11
BIT 6 . . . 1
13
3
13
LSB IN
MASTER LSB OUT
PORT DATA
Figure A-12. SPI Master Timing (CPHA=1)
In Table A-28 the timing characteristics for master mode are listed.
Table A-28. SPI Master Mode Timing Characteristics
Num C
Characteristic
1
P SCK Frequency
1
P SCK Period
2
D Enable Lead Time
3
D Enable Lag Time
4
D Clock (SCK) High or Low Time
5
D Data Setup Time (Inputs)
6
D Data Hold Time (Inputs)
9
D Data Valid after SCK Edge
10 D Data Valid after SS fall (CPHA=0)
11 D Data Hold Time (Outputs)
12 D Rise and Fall Time Inputs
13 D Rise and Fall Time Outputs
Symbol
f_sck
t_sck
t_lead
t_lag
t_wsck
t_su
t_hi
t_vsck
t_vss
t_ho
t_rfi
t_rfo
Min
1/2048
2
—
—
—
8
8
—
—
20
—
—
Typ
—
—
1/2
1/2
1/2
—
—
—
—
—
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
A.16.2 Slave Mode
In Figure A-13 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
MC9S12NE64 Data Sheet, Rev. 1.1
536
Freescale Semiconductor