MC9S12NE64V1 Datasheet, PDF (389/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
14.3 Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
14.3.1 Module Memory Map
Table 14-1. INT Memory Map
Address
Offset
0x0015
0x0016
0x001F
Use
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
14.3.2 Register Descriptions
Access
R/W
R/W
R/W
14.3.2.1 Interrupt Test Control Register
7
6
5
4
3
2
R
0
0
0
WRTINT
ADR3
ADR2
W
Reset
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 14-2. Interrupt Test Control Register (ITCR)
1
ADR1
1
0
ADR0
1
Read: See individual bit descriptions
Write: See individual bit descriptions
Table 14-2. ITCR Field Descriptions
Field
Description
4
WRTINT
3:0
ADR[3:0]
Write to the Interrupt Test Registers
Read: anytime
Write: only in special modes and with I-bit mask and X-bit mask set.
0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.
1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers
instead.
Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.
Test Register Select Bits
Read: anytime
Write: anytime
These bits determine which test register is selected on a read or write. The hexadecimal value written here will
be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR[3:0] will
select vectors 0xFFFE–0xFFF0 while a “7” written to ADR[3:0] will select vectors 0xFF7E–0xFF70.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
389