MC9S12NE64V1 Datasheet, PDF (321/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Descriptions
ECIF — Excessive Collision Interrupt Flag
This flag is set if the total number of collisions has exceeded the maximum retransmission count of 15
while in half-duplex mode. The frame is discarded and another START command must be invoked to
commence a new transmission. If not masked (ECIE is set), an excessive collision interrupt is pending
while this flag is set.
1 = Number of collisions exceeds 15.
0 = Number of collisions is 15 or less.
TXCIF — Frame Transmission Complete Interrupt Flag
This flag is set when a transmit frame has been completed. If not masked (TXCIE is set), a frame
transmission complete interrupt is pending while this flag is set.
1 = Frame transmission has been completed.
0 = Frame transmission has not been confirmed.
11.3.2.8 Interrupt Mask (IMASK)
The interrupt mask register provides control over which possible interrupt events are allowed to generate
an interrupt. If the corresponding bits in both IEVENT and IMASK registers are set, an interrupt is
generated and remains active until a 1 is written to the IEVENT bit or a 0 is written to the IMASK bit.
Module Base + $C
15 14 13 12 11 10
9
8
765
4
3
R
0
0
0
RFCIE
BREIE RXEIE RXAOIE RXBOIE RXACIE RXBCIE MMCIE
LCIE ECIE
W
RESET: 0 0 0
0
0
0
0
0
000
0
0
2
1
0
0
0
TXCIE
0
0
0
= Unimplemented or Reserved
Figure 11-9. Interrupt Mask (IMASK)
Read: Anytime.
Write: Anytime.
RFCIE — Receive Flow Control Interrupt Enable
1 = A receive flow control event causes a receive flow control interrupt request.
0 = No interrupt request is generated by this event.
BREIE — Babbling Receive Error Interrupt Enable
1 = A babbling receive error event causes a babbling receive error interrupt request.
0 = No interrupt request is generated by this event.
RXEIE — Receive Error Interrupt Enable
1 = A receive error event causes a receive error interrupt request.
0 = No interrupt request is generated by this event.
RXAOIE — Receive Buffer A Overrun Interrupt Enable
1 = A receive buffer A overrun event causes a receive buffer A overrun interrupt request.
0 = No interrupt request is generated by this event.
RXBOIE — Receive Buffer B Overrun Interrupt Enable
1 = A receive buffer B overrun event causes a receive buffer B overrun interrupt request.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
321