MC9S12NE64V1 Datasheet, PDF(53/554 Page) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

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MC9S12NE64V1 Datasheet, PDF (53/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

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Signal Description

1.2.3.34 PJ7 / KWJ7 / IIC_SCL â Port J I/O Pin 7

PJ7 is a general-purpose I/O pin. When the IIC module is enabled, it becomes the serial clock line

(IIC_SCL) for the IIC module (IIC). It can be conï¬gured to generate an interrupt (KWJ7) causing the

MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ7 pin is conï¬gured as

a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the IIC block description chapter for information about pin conï¬gurations.

1.2.3.35 PJ6 / KWJ6 / IIC_SDA â Port J I/O Pin 6

PJ6 is a general-purpose I/O pin. When the IIC module is enabled, it becomes the serial data line

(IIC_SDL) for the IIC module (IIC). It can be conï¬gured to generate an interrupt (KWJ6) causing the

MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ6 pin is conï¬gured as

a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the IIC block description chapter for information about pin conï¬gurations.

1.2.3.36 PJ3 / KWJ3 / MII_COL â Port J I/O Pin 3

PJ3 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

collision (MII_COL) signal. It can be conï¬gured to generate an interrupt (KWJ3) causing the MCU to exit

stop or wait mode. While in reset and immediately out of reset, the PJ3 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.37 PJ2 / KWJ2 / MII_CRS /â Port J I/O Pin 2

PJ2 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the carrier

sense (MII_CRS) signal. It can be conï¬gured to generate an interrupt (KWJ2) causing the MCU to exit

stop or wait mode. While in reset and immediately out of reset, the PJ2 pin is conï¬gured as a

high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description chapter

and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.38 PJ1 / KWJ1 / MII_MDIO â Port J I/O Pin 1

PJ1 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

Management Data I/O (MII_MDIO) signal. It can be conï¬gured to generate an interrupt (KWH1) causing

the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ1 pin is conï¬gured

as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description

chapter and the EMAC block description chapter for information about pin conï¬gurations.

1.2.3.39 PJ0 / KWJ0 / MII_MDC â Port J I/O Pin 0

PJ0 is a general-purpose I/O pin. When the EMAC MII external interface is enabled, it becomes the

management data clock (MII_MDC) signal. It can be conï¬gured to generate an interrupt (KWJ0) causing

the MCU to exit stop or wait mode. While in reset and immediately out of reset, the PJ0 pin is conï¬gured

as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block description

chapter and the EMAC block description chapter for information about pin conï¬gurations.

MC9S12NE64 Data Sheet, Rev 1.0

Freescale Semiconductor

53

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