MC9S12NE64V1 Datasheet, PDF (520/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Appendix A Electrical Characteristics
And finally the frequency relationship is defined as:
n = ^f--V-f--_r-^C-_e---^Of--- = 2 ⋅ (synr + 1)
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f_C = 10 kHz:
R = ^2-----â‹---^π---K--^â‹--_Φ-n-----^â‹---f--^C-- ^{= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ}
The capacitance C_s can now be calculated as:
C_s = -_π----2_â‹---f--^â‹_C---^ζ--_â‹-²--R--- ≈ ^0-f--_C-.--5--_â‹-1--R-6--;(ζ = 0.9) ^{= 5.19nF =~ 4.7nF}
The capacitance C_p should be chosen in the range of:
C_s ⁄ 20 ≤ C_p ≤ C_s ⁄ 10
C_p = 470pF
A.12.3.1.1 Jitter Information
The basic functionality of the PLL is shown in Figure 18-22. With each transition of the clock f_cmp, the
deviation from the reference clock f_ref is measured and input voltage to the VCO is adjusted accordingly.
The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage,
temperature, and other factors cause slight variations in the control loop resulting in a clock jitter. This
jitter affects the real minimum and maximum clock periods as illustrated in Figure 18-23.
0
1
2
3
N-1
N
t_min1
t_nom
t_max1
t_minN
t_maxN
Figure 18-23. Jitter Definitions
MC9S12NE64 Data Sheet, Rev. 1.1
520
Freescale Semiconductor