MC9S12NE64V1 Datasheet, PDF (308/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.1.2 Block Diagram
MCU
INTERFACE
RAM
INTERFACE
SIGNALS
EMAC
RX BUFFER A
INTERFACE
RX BUFFER B
INTERFACE
RAM
INTERFACE
SIGNALS
MAC FLOW CONTROL
TX BUFFER
INTERFACE
IP BUS
SIGNALS
IP BUS
REGISTERS
RECEIVER
TRANSMITTER
MII
MANAGEMENT
MII
INTERFACE
MII_RXCLK
MII_RXDV
MII_RXD[3:0]
MII_RXER
MII_TXCLK
MII_TXEN
MII_TXD[3:0]
MII_TXER
MII_CRS
MII_COL
MII_MDC
MII_MDIO
Figure 11-1. EMAC Block Diagram
11.2 External Signal Description
The EMAC module supports the medium-independent interface (MII) which requires 18 input/output
(I/O) pins. The transmit and receive functions require seven signals each (four data signals, a delimiter,
error, and clock). In addition, there are two signals which indicate the status of the media (one indicates
the presence of a carrier and the other indicates that a collision has occurred). The MII management
function requires the remaining two signals, MII_MDC and MII_MDIO. Each MII signal is described
below. These signals are available externally only when the EMAC is enabled in external PHY mode. MII
signals are available only in certain MCU modes.
MC9S12NE64 Data Sheet, Rev. 1.1
308
Freescale Semiconductor