MC9S12NE64V1 Datasheet, PDF (127/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

3.3.2.5 Port J Registers
Memory Map and Register Descriptions
3.3.2.5.1 I/O Register (PTJ)
Module Base + $20
Bit 7
6
5
Read:
PTJ7
PTJ6
0
Write:
EMAC
—
—
IIC IIC_SCL IICSDA
KWU
KWJ
Reset:
0
0
—
4
3
2
1
Bit 0
0
PTJ3
PTJ2
PTJ1
PTJ0
MII_COL MII_CRS MII_MDIO MII_MDC
—
—
—
—
KWJ
—
0
0
0
0
= Reserved or unimplemented
Figure 3-31. Port J I/O Register (PTJ)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EMAC MII external interface and IIC take precedence over general-purpose I/O function. If the
EMAC MII external interface is enabled in external PHY mode, PJ[3:0] pins become MII_MDC,
MII_MDIO, MII_CRS, MII_COL. If IIC is enabled, PJ[7:6] pins become IIC_SDA and IIC_SCL. Please
refer to the EMAC and IIC block description chapters for details.
3.3.2.5.2 Input Register (PTIJ)
Module Base + $21
Bit 7
6
5
Read: PTIJ7
PTIJ6
0
Write:
Reset:
—
—
—
4
3
2
1
Bit 0
0
PTIJ3
PTIJ2
PTIJ1
PTIJ0
—
—
—
—
—
= Reserved or unimplemented
Figure 3-32. Port J Input Register (PTIJ)
Read:Anytime.
Write: writes to this register have no effect.
This register always reads back the status of the associated pins. This can be used to detect overload or
short circuit conditions on output pins.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
127