MC9S12NE64V1 Datasheet, PDF (543/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Introduction
Appendix B
Schematic and PCB Layout Design Recommendations
B.1 Introduction
This sections provides recommendations for schematic and PCB layout design for implementing an
Ethernet interface with the MC9S12NE64 microcontroller unit (MCU).
B.1.1 Schematic Designing with the MC9S12NE64 and Adding an
Ethernet Interface
Figure B-1 is a schematic of a MC9S12NE64 80-pin package minimum system implementation
configured in normal-chip mode and utilizing the internal voltage regulator. This configuration is the
recommended implementation for the MC9S12NE64. The schematic provides a reference for the
following MC9S12NE64 design items.
• Operation mode
• Clocks
• Power
• Ethernet, high-speed LAN magnetics isolation module, and RJ45 Ethernet connector
• EPHY status indicators
• Background debug connector (J1)
To configure the MC9S12NE64 in normal single-chip mode, the MODC, MODB, and MODA pins should
be configured as documented in the device overview chapter of this book.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
543