MC9S12NE64V1 Datasheet, PDF (519/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Reset, Oscillator, and PLL Electrical Characteristics
C_p
V_DDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
∆
K_Φ
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure 18-22. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K₁, f₁ and i_ch from Table A-13.
The grey boxes show the calculation for f_VCO = 50 MHz and f_ref = 1 MHz. E.g., these frequencies are used
for f_OSC = 4 MHz and a 25 MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o-}₌^--) _{–100 ⋅ e}^{(---6---–0---1-–--0---50---0---}₌^-) _-90.48MHz/V
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
= 316.7Hz/Ω
i_ch is the current in tracking mode.
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
f_C < ----------2-----^â‹---^ζ----^â‹---f--^r--^e---^f----------
π
⋅
⎛
⎝
ζ
+
1 + ζ²_⎠⎞
--¹---
10
→
f_C
<
4^---f--r⋅^--e-1^--f-0^{- ;(ζ}
=
0.9 )
f_C < 25kHz
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
519