MC9S12NE64V1 Datasheet, PDF (367/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Functional Description
FEFLTD — Far End Fault Disable
1 = Far end fault detect is disabled
0 = Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation
is disabled
MIILBO — MII Loopback Disable
1 = Disable MII loopback
0 = MII transmit data is looped back to the MII receive pins
JBDE — Jabber Detect Enable (10BASE-T)
1 = Enable jabber detection
0 = Disable jabber detection
LNKTSTD — Link Test Disable (10BASE-T)
1 = Disable 10BASE-T link integrity test
0 = 10BASE-T link integrity test enabled
POLCORD — Disable Polarity Correction (10BASE-T)
1 = 10BASE-T receive polarity correction is disabled
0 = 10BASE-T receive polarity is automatically corrected
ALGD — Disable Alignment
1 = Un-aligned mode. Available only in symbol mode
0 = Aligned mode
ENCBYP — Encoder Bypass
1 = Symbol mode and bypass 4B/5B encoder and decoder
0 = Normal mode
SCRBYP — Scrambler Bypass Mode (100BASE-TX)
1 = Bypass the scrambler and de-scrambler
0 = Normal
TRDANALB — Transmit and Receive Disconnect and Analog Loopback
1 = High-impedance twisted pair transmitter. Analog loopback mode overrides and forces this bit
0 = Normal operation
TRTST — Transmit and Receive Test (100BASE-TX)
1 = Transmit and receive data regardless of link status
0 = Normal operation
12.4 Functional Description
The EPHY is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The EPHY can be configured
to support 10BASE-T or 100BASE-TX applications. The EPHY is configurable via internal registers
which are accessible through the MII management interface as well as limited configurability using the
EPHY register map.
There are five basic modes of operation for the EPHY:
• Power down/initialization
• Auto-negotiate
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
367