MC9S12NE64V1 Datasheet, PDF (222/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 7 Analog-to-Digital Converter (ATD10B8CV3)
7.3.2.8 Reserved Register (ATDTEST0)
7
6
5
4
3
2
1
0
R
U
U
U
U
U
U
U
U
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-10. Reserved Register (ATDTEST0)
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
NOTE
Writing to this register when in special modes can alter functionality.
7.3.2.9 ATD Test Register 1 (ATDTEST1)
This register contains the SC bit used to enable special channel conversions.
7
6
5
4
3
2
R
U
U
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-11. ATD Test Register 1 (ATDTEST1)
1
0
0
SC
0
0
Read: Anytime, returns unpredictable values for Bit7 and Bit6
Write: Anytime
Table 7-18. ATDTEST1 Field Descriptions
Field
0
SC
Description
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC,
CB and CA of ATDCTL5. Table 7-19 lists the coding.
0 Special channel conversions disabled
1 Special channel conversions enabled
Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result
in unpredictable ATD behavior.
Table 7-19. Special Channel Select Coding
SC
CC
CB
1
0
X
1
1
0
1
1
0
1
1
1
1
1
1
CA
Analog Input Channel
X
Reserved
0
V_RH
1
V_RL
0
(V_RH+V_RL) / 2
1
Reserved
MC9S12NE64 Data Sheet, Rev. 1.1
222
Freescale Semiconductor