MC9S12NE64V1 Datasheet, PDF (484/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 18 Debug Module (DBGV1)
Table 18-14. DBGC2 Field Descriptions (continued)
Field
1
RWCEN
0
RWC
Description
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for comparator C. RWCEN is not useful for tagged breakpoints.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
18.3.2.8 Debug Control Register 3 (DBGC3)
7
R
BKAMBH¹
W
6
BKAMBL¹
5
BKBMBH²
4
BKBMBL²
3
RWAEN
2
RWA
Reset
0
0
0
0
0
0
1 _{In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s.}
2 _{In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.}
Figure 18-14. Debug Control Register 3 (DBGC3)
1
RWBEN
0
0
RWB
0
Table 18-15. DBGC3 Field Descriptions
Field
Description
7:6
Breakpoint Mask High Byte for First Address — In dual or full mode, these bits may be used to mask (disable)
BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in
Table 18-16.
The x:0 case is for a full address compare. When a program page is selected, the full address compare will be
based on bits for a 20-bit compare. The registers used for the compare are {DBGCAX[5:0], DBGCAH[5:0],
DBGCAL[7:0]}, where DBGAX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU
address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit
compare. The registers used for the compare are {DBGCAH[7:0], DBGCAL[7:0]} which corresponds to CPU
address [15:0].
Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several
physical addresses may match with a single logical address. This problem may be avoided by using DBG
mode to generate breakpoints.
The 1:0 case is not sensible because it would ignore the high order address and compare the low order and
expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKAMBH
control bit).
The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes
sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCAX compares.
MC9S12NE64 Data Sheet, Rev. 1.1
484
Freescale Semiconductor