MC9S12NE64V1 Datasheet, PDF (303/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Initialization/Application Information
10.7.1.4 Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.
MASTX
END
EMASTX
TST
BEQ
BRSET
MOVB
DEC
BRA
BCLR
RTI
TXCNT
END
IBSR,#$01,END
DATABUF,IBDR
TXCNT
EMASTX
IBCR,#$20
;GET VALUE FROM THE TRANSMITING COUNTER
;END IF NO MORE DATA
;END IF NO ACK
;TRANSMIT NEXT BYTE OF DATA
;DECREASE THE TXCNT
;EXIT
;GENERATE A STOP CONDITION
;RETURN FROM INTERRUPT
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)
before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be
generated first. The following is an example showing how a STOP signal is generated by a master receiver.
MASR
LAMAR
ENMASR
NXMAR
DEC
BEQ
MOVB
DEC
BNE
BSET
BRA
BCLR
MOVB
RTI
RXCNT
ENMASR
RXCNT,D1
D1
NXMAR
IBCR,#$08
NXMAR
IBCR,#$20
IBDR,RXBUF
;DECREASE THE RXCNT
;LAST BYTE TO BE READ
;CHECK SECOND LAST BYTE
;TO BE READ
;NOT LAST OR SECOND LAST
;SECOND LAST, DISABLE ACK
;TRANSMITTING
;LAST ONE, GENERATE ‘STOP’ SIGNAL
;READ DATA AND STORE
10.7.1.5 Generation of Repeated START
At the end of data transfer, if the master continues to want to communicate on the bus, it can generate
another START signal followed by another slave address without first generating a STOP signal. A
program example is as shown.
RESTART
BSET
MOVB
IBCR,#$04
CALLING,IBDR
;ANOTHER START (RESTART)
;TRANSMIT THE CALLING ADDRESS;D0=R/W
10.7.1.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check
if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive
mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR
clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end
of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers
will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave
transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between
byte transfers, SCL is released when the IBDR is accessed in the required mode.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
303