MC9S12NE64V1 Datasheet, PDF (219/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
7.3.2.6 ATD Control Register 5 (ATDCTL5)
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this
register will abort current conversion sequence and start a new conversion sequence.
7
6
5
4
3
R
0
DJM
DSGN
SCAN
MULT
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
2
1
0
CC
CB
CA
0
0
0
Figure 7-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
Table 7-13. ATDCTL5 Field Descriptions
Field
Description
7
DJM
Result Register Data Justification — This bit controls justification of conversion data in the result registers.
See Section 7.3.2.13, “ATD Conversion Result Registers (ATDDRx),” for details.
0 Left justified data in the result registers
1 Right justified data in the result registers
6
DSGN
Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned
conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed
data is not available in right justification. See Section 7.3.2.13, “ATD Conversion Result Registers (ATDDRx),”
for details.
0 Unsigned data representation in the result registers
1 Signed data representation in the result registers
Table 7-14 summarizes the result data formats available and how they are set up using the control bits.
Table 7-15 illustrates the difference between the signed and unsigned, left justified output codes for an input
signal range between 0 and 5.12 Volts.
5
SCAN
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
4
MULT
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C,
S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control
bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection
code.
0 Sample only one channel
1 Sample across several channels
2–0
CC, CB, CA
Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are
sampled and converted to digital codes. Table 7-16 lists the coding used to select the various analog input
channels. In the case of single channel scans (MULT = 0), this selection code specified the channel examined.
In the case of multi-channel scans (MULT = 1), this selection code represents the first channel to be examined
in the conversion sequence. Subsequent channels are determined by incrementing channel selection code;
selection codes that reach the maximum value wrap around to the minimum value.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
219