MC9S12NE64V1 Datasheet, PDF (112/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 3 Port Integration Module (PIM9NE64V1)
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
3.3.2 Register Descriptions
The following table summarizes the effect on the various configuration bits - data direction (DDR), input
/ output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS) and interrupt enable (IE) for
the ports. The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Table 3-3. Pin Configuration Summary
DDR IO RDR PE
PS
IE¹
Function
Pull Device Interrupt
0
X
X
0
X
0
X
X
1
0
0
X
X
1
1
0
X
X
0
0
0
X
X
0
1
0
X
X
1
0
0
X
X
1
1
1
0
0
X
X
1
1
0
X
X
1
0
1
X
X
1
1
1
X
X
1
0
0
X
0
1
1
0
X
1
1
0
1
X
0
1
1
1
X
1
1 _{Applicable only on ports G, H, and J.}
0
Input
Disabled
Disabled
0
Input
Pull Up
Disabled
0
Input
Pull Down
Disabled
1
Input
Disabled Falling edge
1
Input
Disabled
Rising edge
1
Input
Pull Up
Falling edge
1
Input
Pull Down Rising edge
0
Output, full drive to 0
Disabled
Disabled
0
Output, full drive to 1
Disabled
Disabled
0
Output, reduced drive to 0
Disabled
Disabled
0
Output, reduced drive to 1
Disabled
Disabled
1
Output, full drive to 0
Disabled Falling edge
1
Output, full drive to 1
Disabled
Rising edge
1
Output, reduced drive to 0
Disabled Falling edge
1
Output, reduced drive to 1
Disabled
Rising edge
NOTE
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
MC9S12NE64 Data Sheet, Rev. 1.1
112
Freescale Semiconductor