MC9S12NE64V1 Datasheet, PDF (398/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 15 Multiplexed External Bus Interface (MEBIV3)
.
Table 15-1. External System Pins Associated With MEBI
Pin Name
BKGD/MODC/
TAGHI
PA7/A15/D15/D7
thru
PA0/A8/D8/D0
PB7/A7/D7
thru
PB0/A0/D0
PE7/NOACC
PE6/IPIPE1/
MODB/CLKTO
PE5/IPIPE0/MODA
Pin Functions
MODC
BKGD
TAGHI
PA7–PA0
A15–A8
D15–D8
D15/D7
thru
D8/D0
PB7–PB0
A7–A0
D7–D0
PE7
NOACC
MODB
PE6
IPIPE1
CLKTO
MODA
PE5
IPIPE0
Description
At the rising edge on RESET, the state of this pin is registered into the MODC
bit to set the mode. (This pin always has an internal pullup.)
Pseudo open-drain communication pin for the single-wire background debug
mode. There is an internal pull-up resistor on this pin.
When instruction tagging is on, a 0 at the falling edge of E tags the high half of
the instruction word being read into the instruction queue.
General-purpose I/O pins, see PORTA and DDRA registers.
High-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
High-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (IVIS = 1)
in emulation expanded narrow mode. Direction of data transfer is generally
indicated by R/W.
Alternate high-order and low-order bytes of the bidirectional data lines
multiplexed during ECLK high in expanded narrow modes and narrow accesses
in wide modes. Direction of data transfer is generally indicated by R/W.
General-purpose I/O pins, see PORTB and DDRB registers.
Low-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
Low-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (with
IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is
generally indicated by R/W.
General-purpose I/O pin, see PORTE and DDRE registers.
CPU No Access output. Indicates whether the current cycle is a free cycle. Only
available in expanded modes.
At the rising edge of RESET, the state of this pin is registered into the MODB
bit to set the mode.
General-purpose I/O pin, see PORTE and DDRE registers.
Instruction pipe status bit 1, enabled by PIPOE bit in PEAR.
System clock test output. Only available in special modes. PIPOE = 1 overrides
this function. The enable for this function is in the clock module.
At the rising edge on RESET, the state of this pin is registered into the MODA
bit to set the mode.
General-purpose I/O pin, see PORTE and DDRE registers.
Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
MC9S12NE64 Data Sheet, Rev. 1.1
398
Freescale Semiconductor