MC9S12NE64V1 Datasheet, PDF (457/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Functional Description
HARDWARE
READ
HARDWARE
WRITE
FIRMWARE
READ
FIRMWARE
WRITE
GO,
TRACE
8 BITS
AT ∼16 TC/BIT
COMMAND
16 BITS
AT ∼16 TC/BIT
ADDRESS
150-BC
DELAY
16 BITS
AT ∼16 TC/BIT
DATA
NEXT
COMMAND
COMMAND
ADDRESS
DATA
150-BC
DELAY
NEXT
COMMAND
44-BC
DELAY
COMMAND
DATA
NEXT
COMMAND
COMMAND
DATA
32-BC
DELAY
NEXT
COMMAND
COMMAND
64-BC
DELAY
NEXT
COMMAND
Figure 17-6. BDM Command Structure
BC = BUS CLOCK CYCLES
TC = TARGET CLOCK CYCLES
17.4.6 BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 17.3.2.1, “BDM Status Register (BDMSTS).” This clock will be referred to as the target clock in
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Because R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 17-7 and that of target-to-host in Figure 17-8 and
Figure 17-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge.
Because the host and target are operating from separate clocks, it can take the target system up to one full
clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time
while the host measures delays from the point it actually drove BKGD low to start the bit up to one target
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
457