MC9S12NE64V1 Datasheet, PDF (225/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Memory Map and Register Definition
7.3.2.13 ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the
result registers based on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
7.3.2.13.1 Left Justified Result Data
7
R BIT 9 MSB
R BIT 7 MSB
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
3
BIT 5
BIT 3
2
BIT 4
BIT 2
1
BIT 3
BIT 1
0
BIT 2
BIT 0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
10-bit data
8-bit data
R
R
W
Reset
7
6
5
4
3
2
1
0
BIT 1
BIT 0
0
0
0
0
0
0
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
7.3.2.13.2 Right Justified Result Data
R
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BIT 9 MSB BIT 8 10-bit data
0
0
0
0
0
0
0
0
8-bit data
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
7
R BIT 7
R BIT 7 MSB
6
BIT 6
BIT 6
5
BIT 5
BIT 5
4
BIT 4
BIT 4
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
BIT 3
BIT 3
0
2
BIT 2
BIT 2
0
1
BIT 1
BIT 1
0
0
BIT 0
BIT 0
10-bit data
8-bit data
0
Figure 7-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
225