MC9S12NE64V1 Datasheet, PDF (114/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Chapter 3 Port Integration Module (PIM9NE64V1)
Read:Anytime.
Write:Anytime.
This register configures each port T pin as either input or output.
The standard TIM module forces the I/O state to be an output for each port pin associated with an enabled
output compare. When the pin is configured as an output compare the corresponding data direction register
(DDRT) bits do not have any effect on the I/O direction of the pin, and will maintain their previously
latched value. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. If a pin is being used as a timer input capture, the DDRT remains in control of
the pin’s I/O direction and the timer monitors the state of the pin.
DDRT[7:4] — Data Direction Port T
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
PTT or PTIT registers, when changing the DDRT register.
3.3.2.1.4 Reduced Drive Register (RDRT)
Module Base + $3
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
Write: ^{RDRT7 RDRT6 RDRT5 RDRT4}
Reset:
0
0
0
0
—
—
—
—
= Reserved or unimplemented
Figure 3-5. Port T Reduced Drive Register (RDRT)
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRT[7:4] — Reduced Drive Port T
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
MC9S12NE64 Data Sheet, Rev. 1.1
114
Freescale Semiconductor