MC9S12NE64V1 Datasheet, PDF (43/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

Signal Description
1.2.2 Signal Properties Summary
Table 1-4. Signal Properties (Sheet 1 of 4)
orig. order
80 Pin
No.
112 Pin
No.
28
1
1
29
2
2
30
3
3
31
4
4
32
5
5
33
6
6
34
7
7
40
8
8
39
9
9
15
—
10–13
16–19
62
10
14
63
11
15
38
12
20
37
13
21
27
14
22
26
15
23
Pin
Name
Function
1
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ0
PJ1
PB[7:0]
VDDX1
VSSX1
PJ2
PJ3
PG0
PG1
Pin
Name
Function
2
Pin
Name
Function
3
Power
Domain
Internal Pull
Resistor
CTRL
Reset
State
Description
Reset
State
KWH6
MII_TXER
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
error; interrupt
Input
KWH5
MII_TXEN
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
enable; interrupt
Input
KWH4
MII_TXCLK
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
clock; interrupt
Input
KWH3
MII_TXD3
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
data; interrupt
Input
KWH2
MII_TXD2
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
data; interrupt
Input
KWH1
MII_TXD1
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
data; interrupt
Input
KWH0
MII_TXD0
VDDX
PERH/
PPSH
Port H I/O pin;
Disabled EMAC MII transmit
data; interrupt
Input
KWJ0
MII_MDC
VDDX
PERJ/
PPSJ
Port J I/O pin; EMAC
Disabled MII management
data clock; interrupt
Input
KWJ1
MII_MDIO
VDDX
PERJ/
PPSJ
Port J I/O pin; EMAC
Disabled MII management
data I/O; interrupt
Input
ADDR[7:0]
/
—
DATA[7:0]
VDDX
Port B I/O pin;
PUCR Disabled multiplexed
address/data
Input
—
—
See Table 1-5
—
—
See Table 1-5
KWJ2
MII_CRS
VDDX
PERJ/
PPSJ
Port J I/O pin; EMAC
Disabled MII carrier sense;
interrupt
Input
KWJ3
MII_COL
VDDX
PERJ/
PPSJ
Port J I/O pin; EMAC
Disabled MII collision;
interrupt
Input
KWG0
MII_RXD0
VDDX
PERG/
PPSG
Port G I/O pin;
Disabled EMAC MII receive
data; interrupt
Input
KWG1
MII_RXD1
VDDX
PERG/
PPSG
Port G I/O pin;
Disabled EMAC MII receive
data; interrupt
Input
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
43