MC9S12NE64V1 Datasheet, PDF (21/554 Pages) Freescale Semiconductor, Inc – MC9S12NE64V1 Data Sheet

— Clock monitor
— Pierce oscillator
— Phase-locked loop clock frequency multiplier
— Limp home mode in absence of external clock
— 25-MHz crystal oscillator reference clock
• Operating frequency
— 50 MHz equivalent to 25 MHz bus speed for single chip
— 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
• Internal 2.5-V regulator
— Supports an input voltage range from 3.3 V ± 5%
— Low-power mode capability
— Includes low-voltage reset (LVR) circuitry
• 80-pin TQFP-EP or 112-pin LQFP package
— Up to 70 I/O pins with 3.3 V input and drive capability (112-pin package)
— Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
• Development support
— Single-wire background debug™ mode (BDM)
— On-chip hardware breakpoints
— Enhanced DBG debug features
Introduction
1.1.2 Modes of Operation
• Normal modes
— Normal single-chip mode
— Normal expanded wide mode¹
— Normal expanded narrow mode¹
— Emulation expanded wide mode¹
— Emulation expanded narrow mode¹
• Special operating modes
— Special single-chip mode with active background debug mode
• Each of the above modes of operation can be configured for three low-power submodes
— Stop mode
— Pseudo stop mode
— Wait mode
• Secure operation, preventing the unauthorized read and write of the memory contents²
1.MEBI is available only in the 112-pin package and specified at a maximum speed of 16 MHz. If using MEBI from
2.5 MHz to 16 MHz, only 10BASE-T communication is available.
2.No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying
the FLASH difficult for unauthorized users.
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
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