MC68LC302 Datasheet, PDF (96/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

SECTION 5
SIGNAL DESCRIPTION
This section defines the MC68LC302 pinout. The input and output signals of the
MC68LC302 are organized into functional groups and are described in the following sec-
tions. The MC68LC302 is offered in a 100-lead thin quad flat package (TQFP) and a 132-
pin (13 x 13) pin grid array (PGA) for emulator applications.
The MC68LC302 uses a M68000 like bus for communication between both on-chip and ex-
ternal peripherals. This bus is a single, continuous bus existing both on-chip and off-chip the
MC68LC302. Any access made internal to the device is visible externally. Any access made
external is visible internally. Thus, when the M68000 core accesses the dual-port RAM, the
bus signals are driven externally. Likewise, in disable CPU mode, when an external device
accesses an area of external system memory, the chip-select logic can be used to generate
the chip-select signal and DTACK.
5.1 FUNCTIONAL GROUPS
The input and output signals of the MC68LC302 are organized into functional groups as
shown in Table 5-1 and Figure 5-1.
Table 5-1. Signal Definitions (TQFP)
Functional Group
Clocks
System Control
Address Bus
Data Bus/PNIO
Data Bus
Bus Control
Interrupt Control (Bus Arbitration)
NMSI1/ISDN I/F
NMSI2/PAIO
PAIO/SCP
Timer/PBIO
PBIO
Chip Select
VDD
GND
Signals
Number
XTAL, EXTAL, XFC, CLKO,VCCSYN
5
RESET, HALT, BUSW, DISCPU
4
A19–A1
19
PN15-PN8/D15-D8
8
D7-D0
8
AS,OE(R/W),WEH(UDS/A0),WEL(LDS/DS), DTACK
5
IPL2–IPL0(BR, BG, BGACK)
3
RXD1, TXD1, RCLK1, TCLK1, CD1, CTS1, RTS1
7
RXD2, TXD2, RCLK2, TCLK2, CD2, CTS2, RTS2, BRG2
8
SPRXD, SPTXD,SPCLK, MODCLK/PA12
4
TIN1, TIN2, TOUT2, WDOG
4
PB11–PB8
4
CS3–CS0
4
6
11
MOTOROLA
MC68LC302 REFERENCE MANUAL
5-1