MC68LC302 Datasheet, PDF (53/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
NOTE
The ERR bit is set if the user drives the IPL2–IPL0 lines to inter-
rupt level 4 and no INRQ interrupt is pending.
15
14
13
12
11
10
9
8
PB11
PB10
SCC1
SDMA
IDMA
SCC2
TIMER1
—
7
6
5
4
3
2
1
0
PB9
TIMER2
SCP
TIMER3
SMC1
SMC2
PB8
ERR
3.5.2.3 Interrupt Mask Register (IMR)
Each bit in the 16-bit IMR corresponds to an INRQ interrupt source. The user masks an in-
terrupt source by clearing the corresponding bit in the IMR.
15
14
13
12
11
10
9
8
PB11
PB10
SCC1
SDMA
IDMA
SCC2
TIMER1
—
7
6
5
4
3
2
1
0
PB9
TIMER2
SCP
TIMER3
SMC1
SMC2
PB8
—
3.5.2.4 Interrupt In-Service Register (ISR)
Each bit in the 16-bit ISR corresponds to an INRQ interrupt source. In a vectored interrupt
environment, the interrupt controller sets the ISR bit when the vector number corresponding
to the INRQ interrupt source is passed to the core during an interrupt acknowledge cycle.
The user's interrupt service routine should clear this bit during the servicing of the interrupt.
3-16
MC68LC302 REFERENCE MANUAL
MOTOROLA