MC68LC302 Datasheet, PDF (63/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
the corresponding bits in the Chip Select registers to zero, or
mask off those address bits.
Also FC2-0 are driven to 5, so we suggest that the function code
comparison be turned off.
3.8.1 Chip-Select Registers
Each of the four chip-select units has two registers that define its specific operation. These
registers are a 16-bit base register (BR) and a 16-bit option register (OR) (e.g., BR0 and
OR0). The BR should normally be programmed after the OR since the BR contains the chip-
select enable bit.
3.8.1.1 Base Register (BR3–BR0)
These 16-bit registers consist of a base address field, a read-write bit, and a function code
field.
15
13
12
FC2 –FC0
BASE ADDRESS (A23–A13)
2
1
0
RW EN
FC2–FC0 —Function Code Field
This field is contained in bits 15–13 of each BR. These bits are used to set the address
space function code. Because of the priority mechanism and the EN bit, only the CS0 line
is active after a system reset.
Bits 12–2—Base Address
These bits are used to set the starting address of a particular address space.
RW—Read/Write
0 = The chip-select line is asserted for read operations only.
1 = The chip-select line is asserted for write operations only.
EN—Enable
0 = The chip-select line is disabled.
1 = The chip-select line is enabled.
After system reset, only CS0 is enabled; CS3–CS1 are disabled. In disable CPU mode,
CS3–CS0 are disabled at system reset. The chip select does not require disabling before
changing its parameters.
3.8.1.2 Option Registers (OR3–OR0)
These four 16-bit registers consist of a base address mask field, a read/write mask bit, a
compare function code bit, and a DTACK generation field.
15
13
12
DTACK
BASE ADDRESS MASK (M23–M13)
2
1
0
MRW CFC
3-26
MC68LC302 REFERENCE MANUAL
MOTOROLA