MC68LC302 Datasheet, PDF (66/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
ership, the external master can not access the internal IMP registers or RAM. Chip selects
and system control functions, such as the hardware watchdog, continue to operate.
When an external master desires to gain ownership, the following bus arbitration protocol
should be used:
1. Assert HALT.
2. Wait two system clocks.
3. If AS is negated go to step 5.
4. Wait for AS negation. Then wait two additional system clocks.
5. Execute Access (now the bus is guaranteed to be threestated)
6. When done, threestate bus and negate HALT.
NOTE
The RMCST bit in the SCR should be zero for this arbitration
procedure to work correctly.
Also, the external master cannot access the internal address
space of the MC68LC302.
Bus Arbitration is not supported when the MC68LC302 is in one
of the low power modes. The chip does not release the address
and data lines.
3.9 DYNAMIC RAM REFRESH CONTROLLER
The communications processor (CP) main (RISC) controller may be configured to handle
the dynamic RAM (DRAM) refresh task without any intervention from the M68000 core. Use
of this feature requires a timer or SCC baud rate generator (either from the IMP or external-
ly), the I/O pin PB8, and two transmit buffer descriptors from SCC2 (Tx BD6 and Tx BD7).
No changes have been made to the DRAM controller. For more information, please refer to
the MC68302 Users’ Manual.
MOTOROLA
MC68LC302 REFERENCE MANUAL
3-29