MC68LC302 Datasheet, PDF (100/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
XFC—IMP External Filter Capacitor
This pin is a connection for an external capacitor to filter the PLL.
MODCLK/PA12—Clock Mode Select
The state of this input signal along with VCCSYN during reset selects whether the PLL is
enabled and the type of external clock that is used by the phase locked loop (PLL) in the
clock synthesizer to generate the system clocks. Table 5-2 shows the default values of the
PLL. When the PLL is disabled (VCCSYN=0), this pin functions as PA12. When the PLL is
enabled (VCCSYN1), this pin is sampled as MODCLK at reset.This pin must be valid as long
as RESET and HALT are asserted, and have a hold time of 5ns after RESET and HALT are
negated. After reset, MODCLK/PA12 is a general purpose I/O pin.
Table 5-2. Default Operation Mode of the PLL
VCCSYN MODCLK
0X
10
11
PLL
Disabled
Enabled
Enabled
Multi. Factor
(MF+1)
x
4
401
EXTAL Freq.
(examples)
-
4.192MHz
32.768KHz
CLKIN to the
PLL
=EXTAL
4.192MHz
32.768KHz
LC302 System
Clock
=EXTAL
16.768 MHz
13.14 MHz
VCCSYN—Analog PLL Circuit Power
This pin is dedicated to the LC302 analog PLL circuits and determines whether the PLL is
enabled or not. When this pin is connected to Vcc, the PLL is enabled, and when this pin is
connected to ground, the PLL is disabled. The voltage should be well regulated and the pin
should be provided with an extremely low impedance path to the V_CC power rail. V_CCSYN
should be bypassed to GND by a 0.1µF capacitor located as close as possible to the chip
package.
GNDSYN—Analog PLL Circuits’ Ground
This pin is dedicated to the IMP analog PLL circuits. The pin should be provided with an
extremely low impedance path to ground. GNDSYN should be bypassed to VCCSYN by
a 0.1µF capacitor located as close as possible to the chip package.
5.4 SYSTEM CONTROL PINS
The system control pins are shown in Figure 5-3.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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